Computers are making leap developments and are used in various scenes in the society these days. However, these computers called Neumann types are very weak in processing (e.g., real-time human face recognition) easy for a human because of their characteristics in processing schemes themselves.
To cope with such processing, research has been done on neural networks as operation processing models which mimic the information processing scheme of the brain.
As a model of neurons which form a neural network, generally, output values from a plurality of units (neurons) are weighted by a synaptic weight, and the products are input to a unit corresponding to a neuron. The sum of input values is further nonlinearly converted and output. That is, in a general neural network, desired processing is realized by product-sum operation and nonlinear conversion in each unit and between units.
As neural network architectures using the neuron model, associative memories which connect units that execute the product-sum operation to each other or pattern recognition models which hierarchically connect units that execute the product-sum operation have been proposed conventionally.
A neural network is a superparallel distributed information processing model. When this is executed by a Neumann computer based on sequential processing, the efficiency is very low. Hence, to put a neural network into practical use, it is effective to form an integrated circuit as dedicated hardware.
In forming an integrated circuit, digital processing by a digital circuit is suitable for storage of input data and controllability. However, when an analog operation circuit is used as an operation circuit which implements the above-described product-sum operation or nonlinear conversion, the number of elements can greatly be reduced as compared to a digital operation circuit.
That is, to put a neural network into practical use, it is effective to apply digital circuits and analog circuits to an operation processing unit in which their characteristic features effectively function and ultimately form an integrated circuit in which both the digital and analog circuits are mixed.
In this case, the interface unit which connects a digital circuit and an analog circuit must input/output data in a signal format suitable for a corresponding circuit.
For example, to make a digital memory to hold a PWM (Pulse Width Modulation) signal having information in the pulse width, the PWM signal is converted into a digital value by a pulse width/digital conversion circuit. Then, the PWM signal is input to and held in the digital memory.
In addition, to output an analog voltage value accumulated in a capacitor as a PWM signal, the analog voltage value is converted into a pulse having a time width proportional to the analog voltage value by a comparator and output.
When the above-described methods are combined to temporarily convert an analog voltage into a PWM signal and then cause a pulse width/digital conversion circuit to convert the generated PWM signal into a digital value, A/D conversion can be realized.
As the D/A conversion circuit to convert a digital value into an analog voltage value, a combination of a digital/pulse width conversion circuit, switched current source, and capacitor is often used.
More specifically, a digital value is converted into a pulse whose width has a value proportional to the digital value by the digital/pulse width conversion circuit. The switched current source is turned on/off by the pulse to accumulate charges proportional to the pulse width in the capacitor. Accordingly, the digital value is finally converted into an analog value as the voltage value of the capacitor.
The digital/pulse width conversion circuit in the D/A conversion circuit indicates a circuit which has a function of converting a digital input value into a pulse having a time width proportional to the digital input value. Well-known circuits compare the count value output from a counter operated by a clock with a digital input value and make the pulse output fall when both values coincide (e.g., Japanese Patent Laid-Open No. 4-2222).
FIG. 43 is a block diagram showing an example of a conventional digital/pulse width conversion circuit (FIG. 1 of Japanese Patent Laid-Open No. 4-2222). The conventional digital/pulse width conversion circuit shown in FIG. 43 comprises a strobe detection circuit 101, latch circuit 102, counter 103, digital comparator 104, and JK flip-flop 105.
Upon receiving a strobe signal NOT(STB), the strobe detection circuit 101 outputs timing enable signals E1 and E2 at the leading edge of a first clock CLK. The timing enable signal E1 changes to L level at the leading edge of the next clock. On the other hand, the timing enable signal E2 is always at H level while a clear signal NOT(reset) is at H level.
The latch circuit 102 latches 16 digital data bits D0 to D16 which are output from an external device and outputs them as latch data Q0 to Q15. The 16-bit counter 103 counts the clocks CLK and outputs count values C0 to C15. When the count value reaches FFFF, the counter 103 outputs a count out signal C.O. The digital comparator 104 compares the latch data Q0 to Q15 with the count values C0 to C15. The digital comparator 104 outputs H level to the JK flip-flop 105 until the count values C0 to C15 exceed the latch data Q0 to Q15. When the count values C0 to C15 exceed the latch data Q0 to Q15, the digital comparator 104 inverts the output value to L level.
At the start of the processing cycle, the output signal from the digital comparator 104 is input to an input terminal J of the JK flip-flop 105. An output Q of the JK flip-flop 105 holds H level. At the leading edge of the first clock CLK after the output signal from the digital comparator 104 is inverted to L level, the JK flip-flop 105 inverts the output Q to L level. Upon receiving the count out signal C.O., the JK flip-flop 105 returns the output Q to H level.
With this arrangement, pulses having time widths proportional to the values of the digital data D0 to D16 are output to the output Q of the JK flip-flop 105.
A pulse width/digital conversion circuit will be described next. Conventionally, a pulse width/digital conversion circuit is widely used in an integral A/D converter. Its technical contents are disclosed in, e.g., Yasoji Suzuki & Masahiro Yoshida, “Introduction to Pulse/Digital Circuit”, Nikkan Kogyo Shimbun, issued Jul. 26, 2001, pp. 225–232.
FIG. 44 is a circuit diagram of a conventional pulse width/digital conversion circuit used in an integral A/D converter.
A conventional pulse width/digital conversion circuit 111 has a simple arrangement including an AND gate circuit 112 and counter 113. An input pulse PW which has undergone digital/pulse width conversion and a clock CLK are input to the AND gate circuit 112). The AND gate circuit 112 outputs a gate signal g as the AND of the input pulse PW and clock CLK to the counter 113.
The counter 113 counts the leading edges of the input gate signal g and outputs the count value as an m-bit digital output D={D0, . . . , Dm−1}.
According to this arrangement, when the input pulse PW is at H level, the AND gate 112 is enabled.
When the input pulse PW is at L level, the AND gate 112 is desabled. While the AND gate 112 is enabled, the clock CLK is output as the gate signal g. The counter 113 counts the clock output as the gate signal g. With this operation, a count value proportional to the width of the input pulse PW is obtained as the digital output D={D0, . . . , Dm−1}.
In a product-sum operation circuit which executes multiplication and accumulation in parallel, using a digital/pulse width conversion circuit, a D/A conversion circuit using a digital/pulse width conversion circuit, and an A/D conversion circuit using a pulse width/digital conversion circuit is very effective because their structures are simple.
However, when the digital/pulse width conversion circuit is used in an apparatus which executes digital/pulse width conversion of a number of digital input values in parallel and outputs a modulated pulse, the circuit area and power consumption increase in proportion to the number of digital/pulse width conversion circuits operating in parallel.
To execute digital/pulse width conversion of a number of digital input values in parallel, a plurality of digital/pulse width conversion circuits shown in FIG. 43 are arranged in parallel, and the digital input values are input to the digital/pulse width conversion circuits, respectively. When pulses output from the digital/pulse width conversion circuits are extracted, digital/pulse width conversion can be executed in parallel.
In this case, however, the circuit area of each digital/pulse width conversion circuit increases in proportion to the number of circuits. In addition, the switching operation by the clock is frequently executed. For this reason, when the driving powers of all the digital/pulse width conversion circuits are totaled, a considerably large power is consumed. Hence, in an apparatus such as a portable device which requires downsizing and low power consumption, it is difficult to use digital/pulse width conversion circuits to execute digital/pulse width conversion of a number of digital input values in parallel.
Similarly, when the pulse width/digital conversion circuit shown in FIG. 44 is used in an apparatus which executes pulse width/digital conversion of a number of pulse inputs in parallel and outputs a digital value, the total power consumption of the pulse width/digital conversion circuits 111 is considerably high.
More specifically, when the pulse width/digital conversion circuit 111 shown in FIG. 44 is used for each pulse input, a number of counters 113 execute the switching operation in parallel. For this reason, even when each counter 113 comprises, e.g., a CMOS, the charge/discharge power consumption in charge/discharge of the load capacitance in switching by the counter 113 is high. The increase in charge/discharge power consumption becomes conspicuous as the number of pulse inputs increases.
In addition, when a number of counters 113 operate in parallel, the switching noise of the counters 113 increases. Hence, a measure against noise in the entire circuit is necessary.